Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include, but are not limited to, these exemplary devices and further can include devices that are only partially programmable.
ICs typically suffer from a number of different timing degradations. For example, jitter is one type of timing degradation that refers to a deviation of some aspect of a clock signal within an IC. While jitter can influence many aspects of a circuit design, other timing degradations exist that operate independently of jitter. These timing degradations can result in time delays in data signals as well as variance in the rise and/or fall times of data signals. These timing degradations should be accounted for to better characterize and understand the operation of circuit designs implemented within ICs.